The present invention relates to a solid state imaging apparatus which inhibits the generation of a lateral smear, and reduces the amount of electric current consumed. This solid state imaging apparatus uses a Charge Modulation Device (hereinafter abbreviated as a CMD) as a pixel.
Various solid state imaging apparatuses having been hitherto well known are are composed of imaging elements having MIS-type light receiving/accumulating portions. Among such solid state imaging apparatuses there are solid state imaging apparatuses which utilize imaging elements having MIS-type light receiving/accumulating portions as well as internal amplifying functions. A solid state imaging apparatus which utilizes the CMD imaging element proposed by the applicant of this invention is an example of such solid state imaging apparatuses. This solid state imaging apparatus is disclosed in Japanese Patent Laid-Open No. 61-84059 and in a thesis titled "A NEW MOS IMAGE SENSOR OPERATING IN A NON-DESTRUCTIVE READOUT MODE" on pages 353 to 356 of a collection of theses for the International Electron Device Meeting (IEDM) held in 1986.
A conventional solid state imaging apparatus using such a CMD imaging element will now be described with reference to the circuit configuration of FIG. 1. CMDs 1-11, 1-12 . . . 1-mn, each constituting a pixel, are first arranged in a matrix manner. A video bias V.sub.DD (&gt;0) is applied to the drain of each CMD. The gate terminals of the CMDs arranged in an X direction are respectively connected to row lines 2-1, 2-2 . . . 2-m. The source terminals of the CMDs arranged in a Y direction are respectively connected to bit lines 3-1, 3-2 . . . 3-m. The bit lines 3-1, 3-2 .. 3-m are all connected to a signal line 6 through transistors for selecting a column ( column selecting transistors 4-1, 4-2 . . . 4-n), respectively. Also, the bit lines 3-1, 3-2 . . . 3-m are all connected to a grounded reference line 7 through non-selection transistors 5-1, 5-2 . . . 5-n, respectively. The signal line 6 is connected to a current-voltage conversion type preamplifier 12 whose input is virtually grounded.
The output terminal 9 of the preamplifier 12 reads an image signal having a negative polarity in a time series manner. The row lines 2-1, 2-2 . . . 2-m are connected to a vertical scanning circuit 10. Signals .phi..sub.G1, .phi..sub.G2 . . . .phi..sub.Gm are applied to the row lines 2-1, 2-2 .. 2-m. The gate terminals of the column selecting transistors 4-1, 4-2 . . . 4-n and the non-selection transistors 5-1, 5-2 . . . 5-n are connected to a horizontal scanning circuit 11. Signals .phi..sub.s1, .phi..sub.s2 . . . .phi..sub.Sn and their inversion signals are applied to the column selecting transistors 4-1, 4-2 . . . 4-n and the non-selection transistors 5-1, 5-2 . . . 5-n. All the CMDs are formed on the same substrate to which a substrate voltage V.sub.sub is applied.
The reference line 7 is used for fixing the electric potentials of bit lines which are not selected at the same level as those when a reading operation is performed. It is provided with a function to eliminate the effect caused by the parasitic capacity of each bit line.
FIG. 2 is a view in which the section of a horizontal scanning circuit is selected and shown in detail. FIG. 3 is a timing chart illustrating the operation of the horizontal scanning circuit section. In FIG. 3, reference characters .phi..sub.H1 and .phi..sub.H2 denote clock pulses applied to the horizontal scanning circuit 11, and reference Character .phi..sub.HST denotes a start pulse. Reference characters s-1, s-2 and s-3 denote horizontal selecting signals .phi..sub.S1, .phi..sub.S2 and .phi..sub.S3 applied to the gates of the column selecting transistors 4-1, 4-2 and 4-3, respectively. Reference characters g-1, g-2 and g-3 denote inversion signals applied to the gates of the non-selection transistors 5-1, 5-2 and 5-3, respectively.
The operation of the vertical scanning circuit 10 selects pixels connected to the row lines on which vertical scanning signals have assumed a reading potential. When the horizontal selecting signals .phi..sub.S1, .phi..sub.S2 . . . .phi..sub.Sn, which are output from the horizontal scanning circuit 11, sequentially turn ON the column selecting transistors 4-1, 4-2 . . . 4-n, light accumulating signals of the selected pixels are sequentially output from the output terminal 9 through the signal line 6, as indicated by SIG of FIG. 3.
In the conventionally-constructed solid state imaging apparatus, when intense light is emitted, a pseudo signal "a" (lateral smear) is generated as shown in FIG. 4. In FIG. 4, reference character "b" designates a high-light portion. The following explains how such a lateral smear is generated. Because the reference line 7 is constructed so that bit lines which are not selected are all connected to the reference line 7, when intense light is emitted, an electric current on the order of several mA flows to the reference line 7. As shown in the equivalence circuit diagram of FIG. 5, when such a current flows, the electric potential of the reference line 7 increases because of the parasitic resistance "r" of the reference line 7. The parasitic capacity C.sub.V of each bit line is thereby charged. In the above equivalence circuit, pixels are each indicated by electric current sources i.sub.1, i.sub.2 . . . i.sub.n.
Under the above conditions, when a bit line is selected, the original signal current is overlapped by a discharge current of the bit line parasitic capacity C.sub.v. This generates a lateral smear. When a bright subject is formed into an image on an entire scene, a relatively large amount of an output current of all of the bit lines, except a selected bit line, flows to the reference line. Therefore, a phenomenon similar to the above is also generated.